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features ? transparent rf receiver ics for 315 mhz (a ta5746) and 433.92 mhz (ata5745) with high receiving sensitivity fully integrated pll with low phase noise vco, pll, and loop filter high fsk/ask sensitivity:?105 dbm (ata574 6, fsk, 9.6 kbits/s, manchester, ber 10 -3 ) ?114 dbm (ATA5746, ask, 2.4 kbits/s, manchester, ber 10 -3 ) ?104 dbm (ata5745, fsk, 9.6 kbits/s, manchester, ber 10 -3 ) ?113 dbm (ata5745, ask, 2.4 kbits/s, manchester, ber 10 -3 ) supply current: 6.5 ma in ac tive mode (3v, 25c, ask mode) data rate: 1 kbit/s to 10 kbit s/s manchester ask, 1 kbit/s to 20 kbits/s manchester fsk with four programmable bit rate ranges switching between modulation types ask/fs k and different data rates possible in 1 ms typically, without hardwa re modification on board to allow different modulation schemes for rke, tpms low standby current: 50 a at 3v, 25c ask/fsk receiver uses a low-if architectur e with high selectiv ity, blocking, and low intermodulation (typical 3-db blocking 68.0 dbc at 3 mhz/74.0 dbc at 20.0 mhz, system i1dbcp = ?3 1dbm/system iip3 = ?24dbm) telegram pause up to 52 ms supported in ask mode wide bandwidth agc to handle large out-o f-band blockers above the system i1dbcp 440-khz if frequency with 30-db image rejection and 420-khz if bandwidth to support pll transmitters with standa rd crystals or saw-based transmitters rssi (received signal streng th indicator) with output signal dynamic range of 65 db low in-band sensitivity change of typically 2.0 db within 160-khz center frequency change in the complete te mperature and supply voltage range sophisticated threshold control and quasi-p eak detector circuit in the data slicer fast and stable xto start-up circuit (> ?1.4 k ? worst-case start impedance) clock generation for microcontroller esd protection at all pins (4 kv hbm, 200v mm, 500v fcdm) dual supply voltage range: 2.7v to 3.3v or 4.5v to 5.5v temperature range: ?40c to +105c small 5 mm 5 mm qfn24 package applications automotive keyless entry and tire pressure monitoring systems alarm, telemetering and energy metering systems benefits supports header and blanking periods of protocols common in rke and tpm systems (up to 52 ms in ask mode) all rf relevant functions are integrated. the single-ended rf input is suited for easy adaptation to / 4 or printed-loop antennas allows a low-cost ap plication with only 8 passive components suitable for use in a receiver for joint rke and tpms optimal bandwidth maximizes sensitivity while maintaining saw transmitter compatibility clock output provides an external microc ontroller crystal-prec ision time reference well suited for use with pl l transmitter ata5756/ata5757 uhf ask/fsk receiver ata5745 ATA5746 preliminary 4596a?rke?05/06
2 4596a?rke?05/06 ata5745/ATA5746 [preliminary] 1. general description the ata5745/ATA5746 is a uhf ask/fsk transparent receiver ic with low power consumption supplied in a small qfn24 package (body 5 mm 5 mm, pitch 0.65 mm). ata5745 is used in the 433 mhz to 435 mhz band of operation, and ATA5746 in 313 mhz to 317 mhz. the ic com- bines the functionality of remo te keyless entry (rke - typica lly low bit rate ask) and tire pressure monitoring (tpm - typically high bit rate fsk) into one receiver under the control of an external microcontroller such as an atmega48 (avr ? ). for improved image rejection and selectivity, the if frequency is fixed to 440 khz. the if block uses an 8th-order band pass yielding a receive bandwidth of 420 khz. this enables the use of the receiver in both saw- and pll-based transmitter systems utilizing various types of data-bit encoding such as pulse width modulation, manchester modulati on, variable pulse modulation, pulse position modulation, and nrz. prevailing encryption protocols such as keeloq ? are easily supported due to the receiver?s ability to hold the current data slicer threshold for up to 52 ms when incoming rf telegrams contain a blanking interval. this feature eliminates erroneous noise from appearing on the demodulated data output pin, and simplifies software decoding algorithms. the decoding of the data stream mu st be carried out by a connected microcontroller device. because of the highly integrated design, the only required rf components are for the purpose of receiver antenna matching. ata5745 and ATA5746 supp ort manchester bit rates of 1 kbit/ s to 10 kbits/s in ask and 1 kbit/s to 20 kbits/s in fsk mode. the four discrete bit rate passbands are selectable and cover 1.0 kbit/s to 2.5 kbits/s, 2.0 kbits/s to 5.0 kbits/s, 4.0 kbits/s to 10.0 kbits/s, and 8.0 kbits/s to 10.0 kbits/s or 20.0 kbits/s (for ask or fsk, respectively). the receiver contains an rssi output to provide an indication of received signal strength and a sense input to allow the customer to select a threshold below which the data signal is gated off. ask/fsk and bit rate ranges are selected by the conn ected microcontroller device via pins ask_nfsk, br0, and br1. figure 1-1. system block diagram (lna, mixer, vco, pll, if filter, rssi amp., demodulator) rf receiver ata5745/ATA5746 antenna xto microcontroller microcontroller interface 4 ... 8 power supply digital control logic
3 4596a?rke?05/06 ata5745/ATA5746 [preliminary] figure 1-2. pinning qfn24 table 1-1. pin description pin symbol function 1 test2 test pin, during operation at gnd 2 test1 test pin, during operation at gnd 3 clk_out output to clock a connected microcontroller 4 clk_out_ctrl1 input to control clk_out (msb) 5 clk_out_ctrl0 input to control clk_out (lsb) 6 enable input to enable the xto 7 xtal2 reference crystal 8 xtal1 reference crystal 9 dvcc digital voltage supply blocking 10 vs5v power supply input for voltage range 4.5v to 5.5v 11 vs3v_avcc power supply input for voltage range 2.7v to 3.3v 12 gnd ground 13 lna_gnd rf ground 14 lna_in rf input 15 sense sensitivity control resistor 16 sense_ctrl sensitivity selection low: normal sensitivity, high: reduced sensitivity 17 rssi output of the rssi amplifier 18 test3 test pin, during operation at gnd 19 rx input to activate the receiver 20 br0 bit rate selection, lsb 21 br1 bit rate selection, msb 22 ask_nfsk fsk/ask selection low: fsk, high: ask 23 cdem capacitor to adjust the lower cut-off frequency data filter 24 data_out data output gnd ground/backplane (exposed die pad) test3 data_out br1 rx br0 ask_nfsk cdem xtal2 vs5v gnd v s3v_avcc dvcc xtal1 rssi lna_in lna_gnd sense sense_ctrl test2 789101112 24 13 14 15 16 17 18 6 5 4 3 2 1 23 22 test1 clk_out_ctrl0 enable clk_out_ctrl1 clk_out 21 20 19
4 4596a?rke?05/06 ata5745/ATA5746 [preliminary] figure 1-3. block diagram lpf fsk ask vs3v_avcc vs5v sense_ctrl sense gnd dvcc lna_in lna_gnd cdem ask_nfsk br0 br1 rx clk_out_ctrl1 test1 test3 test2 enable rssi clk_out clk_out_ctrl0 data_out standby logic control xto div. by 3, 6, 12 lpf xtal2 xtal1 xto lna vco pll (/24, /32) if amp if amp ask/fsk demo- dulator power supply data slicer ask/fsk control if filter
5 4596a?rke?05/06 ata5745/ATA5746 [preliminary] 2. rf receiver as seen in figure 1-3 on page 4 , the rf receiver consists of a low-noise amplifier (lna), a local oscillator, and the signal processing part with mixe r, if filter, if amplifier with analog rssi, fsk/ask demodulator, data filter, and data slicer. in receive mode, the lna pre-amplifies the received signal which is converted down to a 440-khz intermediate frequency (if), then filtered and amplified before it is fed into an fsk/ask demodulator, data filter, and data slicer. the rece ived signal strength indicator (rssi) signal is available at the pin rssi. 2.1 low-if receiver the receive path consists of a fully integrated low- if receiver. it fulfills the sensitivity, blocking, selectivity, supply voltage, and supply current sp ecification needed to design an automotive inte- grated receiver for rke and tpm systems. a benefit of the integrated receive filter is that no external components needed. at 315 mhz, the ata5745 receiver (433.92 mhz for the ATA5746 receiver) has a typical system noise figure of 6.0 db (7.0 db), a system i1 dbcp of ?31 dbm (?30 dbm), and a system iip3 of ?24 dbm (?23 dbm). the signal path is linear for out-of-band disturbers up to the i1dbcp and hence there is no agc or switching of the lna needed, and a better blocking performance is achieved. this receiver uses an if (intermediat e frequency) of 440 khz, the typical image rejec- tion is 30 db and the typical 3-db if filter bandwidth is 420 khz (f if = 440 khz 210 khz, f lo_if = 230 khz and f hi_if = 650 khz). the demodulator needs a signal-to-noise ratio of 8.5 db for 10 kbits/s manchester with 38 khz frequency deviation in fsk mode, thus, the resulting sensi- tivity at 315 mhz (433.92 mhz) is typically ?105 dbm (?104 dbm). due to the low phase noise and spurs of the synthesizer together with the 8th-order integrated if filter, the receiver has a better selectivity and blocking performance than more complex double superhet receivers, without using external components and without numerous spurious receiv- ing frequencies. a low-if architecture is also less sensitive to second-order intermodulation (iip2) than direct conversion receivers where every pulse or ampl itude modulated signal (especially the signals from tdma systems like gsm) demodulates to the receiving signal band at second-order non-linearities.
6 4596a?rke?05/06 ata5745/ATA5746 [preliminary] 2.2 input matching at lna_in the measured input impedances as well as the val ues of a parallel equivalent circuit of these impedances can be seen in table 2-1 . the highest sensitivity is achieved with power matching of these impedances to the source impedance. the matching of the lna input to 50 ? is done using the circuit shown in figure 2-1 and the val- ues of the matching elements given in table 2-2 . the reflection coefficients were always ?10 db. note that value changes of c1 and l1 may be necessary to compensate individual board layout parasitics. the measured typical fsk and ask manchester-code sensitivities with a bit error rate (ber) of 10 ?3 are shown in table 2-3 and table 2-4 on page 7 . these measure- ments were done with wire-wound inductors having quality factors reported in table 2-2 , resulting in estimated matching losses of 0.8 db at 315 mhz and 433.92 mhz. these losses can be estimated when calculating the parallel equivalent resistance of the inductor with r loss =2 f l q l and the matching loss with 10 log(1+r in_p /r loss ). figure 2-1. input matching to 50 ? table 2-1. measured input impedances of the lna_in pin f rf [mhz] z in (rf_in) [ ? ]r in_p //c in_p [pf] 315 (72.4 ? j298) 1300 ? //1.60 433.92 (55 ? j216) 900 ? //1.60 table 2-2. input matching to 50 ? f rf [mhz] c 1 [pf] l 1 [nh] q l1 315 2.2 68 20 433.92 2.2 36 15 rf in 14 c1 l1 lna_in ata5745/ATA5746
7 4596a?rke?05/06 ata5745/ATA5746 [preliminary] conditions for the sensitivity measurement: the given sensitivity values ar e valid for manchester-modulated signals. for the sensitivity mea- surement the distance from edge to edge must be evaluated. as can be seen in figure 6-1 on page 24 , in a manchester-modulated data stream, the time segments t ee and 2 t ee occur. to reach the specified sensit ivity for the evaluation of t ee and 2 t ee in the data stream, the following limits should be used (t ee min, t ee max, 2 t ee min, 2 t ee max). 2.3 sensitivity versus supply voltag e, temperature and frequency offset to calculate the behavior of a transmission system, it is important to know the reduction of the sensitivity due to several influences. the most important are frequency offset due to crystal oscillator (xto) and crystal frequency (xtal) errors, temperature and supply voltage depen- dency of the noise figure, and if-filter bandwidth of the receiver. figure 2-2 and figure 2-3 on page 8 show the typical sensitivity at 315 mhz, ask, 2.4 kbits/s and 9.6 kbits/s, manchester, figure 2-4 and figure 2-5 on page 9 show a typical sensitivity at 315 mhz, fsk, 2.4 kbits/s and 9.6 kbits/s, 38 khz, manchester versus the frequency offset between transmitter and receiver at t amb = ?40c, +25c, and +105c and supply voltage vs = vs3v_avcc = vs5v = 2.7v, 3.0v and 3.3v. table 2-3. measured typical sensitivity fsk, 38 khz, manchester, ber = 10 ?3 rf frequency br_range_0 1.0 kbit/s br_range_0 2.5 kbits/s br_range_1 5 kbits/s br_range_2 10 kbits/s br_range_3 10 kbits/s br_range_3 20 kbits/s 315 mhz ?108 dbm ?108 dbm ?107 dbm ?105 dbm ?104 dbm ?104 dbm 433.92 mhz ?107 dbm ?107 dbm ?106 dbm ?104 dbm ?103 dbm ?103 dbm table 2-4. measured typical sens itivity 100% ask, manchester, ber = 10 ?3 rf frequency br_range_0 1.0 kbit/s br_range_0 2.5 kbits/s br_range_1 5 kbits/s br_range_2 10 kbits/s br_range_3 10 kbits/s 315 mhz ?114 dbm ?114 dbm ?113 dbm ?111 dbm ?109 dbm 433.92 mhz ?113 dbm ?113 dbm ?112 dbm ?110 dbm ?108 dbm table 2-5. limits for sensitivity measurements bit rate t ee min t ee typ t ee max 2 t ee min 2 t ee typ 2 t ee max 1.0 kbit/s 260 s 500 s 790 s 800 s 1000 s 1340 s 2.4 kbits/s 110 s 208 s 310 s 320 s 416 s 525 s 5.0 kbits/s 55 s 100 s 155 s 160 s 200 s 260 s 9.6 kbits/s 27 s 52 s 78 s 81 s 104 s 131 s
8 4596a?rke?05/06 ata5745/ATA5746 [preliminary] figure 2-2. measured sensitivit y (315 mhz, ask, 2.4 kbits/s , manchester) versus fre- quency offset figure 2-3. measured sensitivit y (315 mhz, ask, 9.6 kbits/s , manchester) versus fre- quency offset input sensitivity (dbm) at ber < 1e-3, ata 5746, ask, 2.4 kbits/s (manchester), br = 0 -118.00 -117.00 -116.00 -115.00 -114.00 -113.00 -112.00 -111.00 -110.00 -109.00 -108.00 -107.00 -106.00 -105.00 -104.00 -103.00 -300 -200 -100 0 100 200 300 delta rf (khz) at 315 mhz input sensitivity (dbm) 2.7v / -40?c 3.0v / -40?c 3.3v / -40?c 2.7v / 27?c 3.0v / 27?c 3.3v / 27?c 2.7v / 105?c 3.0v / 105?c 3.3v / 105?c input sensitivity (dbm) at ber < 1e-3, ata 5746, ask, 9.6 kbits/s (manchester), br = 2 -115.00 -114.00 -113.00 -112.00 -111.00 -110.00 -109.00 -108.00 -107.00 -106.00 -105.00 -104.00 -103.00 -102.00 -101.00 -100.00 -300 -200 -100 0 100 200 300 delta rf ( khz ) at 315 mhz input sensitivity (dbm) 2.7v / -40?c 3.0v / -40?c 3.3v / -40?c 2.7v / 27?c 3.0v / 27?c 3.3v / 27?c 2.7v / 105?c 3.0v / 105?c 3.3v / 105?c
9 4596a?rke?05/06 ata5745/ATA5746 [preliminary] figure 2-4. measured sensitivity (315 mhz, fsk, 2. 4 kbits/s, 38 khz, manchester) versus frequency offset figure 2-5. measured sensitivity (315 mhz, fsk, 9. 6 kbits/s, 38 khz, manchester) versus frequency offset input sensitivity (dbm) at ber < 1e-3, ata 5746, fsk, 2.4 kbits/s (manchester), br0 -112.00 -111.00 -110.00 -109.00 -108.00 -107.00 -106.00 -105.00 -104.00 -103.00 -102.00 -101.00 -100.00 -99.00 -98.00 -300 -200 -100 0 100 200 300 delta rf (khz) at 315 mhz input sensitivity (dbm) 2.7v / -40?c 3.0v / -40?c 3.3v / -40?c 2.7v / 27?c 3.0v / 27?c 3.3v / 27?c 2.7v / 105?c 3.0v / 105?c 3.3v / 105?c input sensitivity (dbm) at ber < 1e-3, ata 5746, fsk, 9.6 kbits/s (manchester), br = 2 -110.00 -109.00 -108.00 -107.00 -106.00 -105.00 -104.00 -103.00 -102.00 -101.00 -100.00 -99.00 -98.00 -97.00 -96.00 -95.00 -300 -200 -100 0 100 200 300 delta rf (khz) at 315 mhz input sensitivity (dbm) 2.7v / -40?c 3.0v / -40?c 3.3v / -40?c 2.7v / 27?c 3.0v / 27?c 3.3v / 27?c 2.7v / 105? c 3.0v / 105? c 3.3v / 105? c
10 4596a?rke?05/06 ata5745/ATA5746 [preliminary] as can be seen in figure 2-5 on page 9 , the supply voltage has almost no influence. the tem- perature has an influence of about 1.0 db, and a frequency offset of 160 khz also influences by about 1 db. all these influences, combined with the sensitivity of a typical ic (?105 db), are then within a range of ?103.0 dbm and ?107.0 dbm over temperature, supply voltage, and fre- quency offset. the integrated if filter has an additional production tolerance of 10 khz, hence, a frequency offset between the receiver and the transmitter of 160 khz can be accepted for xtal and xto tolerances. note: for the demodulator used in the ata5745/at a5746, the tolerable frequency offset does not change with the data frequency. henc e, the value of 160 khz is valid for 1 kbit/s to 10 kbits/s. this small sensitivity change over supply voltage, frequency offset, and temperature is very unusual in such a receiver. it is achieved by an internal, very fast, and automatic frequency cor- rection in the fsk demodulator after the if filter, which leads to a higher system margin. this frequency correction tracks the input frequency ve ry quickly. if, however, the input frequency makes a larger step (for example, if the system changes between different communication part- ners), the receiver has to be restarted. this can be done by switching back to standby mode and then again to active mode (pin rx 1 0 1) or by generating a positive pulse on pin ask_nfsk (0 1 0). 2.4 frequency accuracy of the crystals in a comb ined rke and tpm system in a tire pressure measurement system working at 315 mhz and using an ata5756 as transmit- ter and an ATA5746 is receiver, the higher frequency tolerances and the tolerance of the frequency deviation of the transmitter has to be considered. in the tpm transmitter, the crystal has a frequency error over temperature ?40c to 125c, aging, and tolerance of 80 ppm (25.2 khz at 315 mhz). the tolerances of the xto, the capacitors used for fsk modulation, and the stray capacitances cause an additional frequency error of 30 ppm (9.45 khz at 315 mhz). the frequency deviation of such a transmitter varies between 16 khz and 24 khz, since a higher frequen cy deviation is equivalent to a frequency error this has to be considered as an additi onal 24 khz ? 19.5 khz = 4.5khz frequency toler- ance (19.5 khz is constant). all tolerances added, these transmitters have a worst-case frequency offset of 39.15 khz. for the receiver in the car, a tolerance of 160 khz ? 39.15 khz = 120.85 khz (383.6 ppm) remains. the needed frequency stability of the crystals over temperature and aging is 383.6 ppm ? 5 ppm = 378.6 ppm. the aging of such a crystal is 10 ppm, leaving a reason- able 368.6 ppm for the temperature dependency of the crystal frequency in the car. since the receiver in the car is able to receive these tpm transmitter signals with high frequency offsets, the component specification in the key can be largely relaxed. this system calculation is based on worst-case tolerances of all the components; this leads in practice to a system with margin. for a 433.92 mhz tpm system using ata5757 as transmitter and ata5745 as receiver, the same calculation must be done, but since the rf frequency is higher, every ppm of crystal toler- ances results in higher frequency offset and either the system must have lower tolerances or a lower margin at this frequency.
11 4596a?rke?05/06 ata5745/ATA5746 [preliminary] 2.5 rx supply current versus te mperature and supply voltage table 2-7 shows the typical supply curr ent of the receiver in active mode versus supply voltage and temperature with vs = vs3v_avcc = vs5v. 2.6 blocking, selectivity as can be seen in figure 2-6 on page 11 , and figure 2-7 and figure 2-8 on page 12 , the receiver can receive signals 3 db higher than the sensitivity level in the presence of large block- ers of ?34.5 dbm or ?28 dbm with small frequency offsets of 3 mhz or 20 mhz. figure 2-6 , and figure 2-7 on page 12 show the narrow-band blocking, and figure 2-8 on page 12 shows the wide-band blocking characteristic. the measurements were done with a useful signal of 315 mhz, fsk, 10 kbits/s, 38 khz, manchester, br_range2 with a level of ?105 dbm + 3 db = ?102 dbm, which is 3 db above the sensitivity level. the figures show how much larger than ?102 dbm a continuous wave signal can be, until the ber is higher than 10 ?3 . the measurements were done at the 50 ? input shown in figure 2-1 on page 6 . at 3 mhz, for example, the blocker can be 67.5 dbc higher than ?102 dbm, or ?102 dbm + 67.5 dbc = ?34.5 dbm. figure 2-6. close-in 3-db blocking characteristic and image response at 315 mhz table 2-6. measured current in active mode ask vs = vs3v_avcc = vs5v 2.7v 3.0v 3.3v t amb = ?40c 5.4 ma 5.5 ma 5.6 ma t amb = 25c 6.4 ma 6.5 ma 6.6 ma t amb = 105c 7.4 ma 7.5 ma 7.6 ma table 2-7. measured current in active mode fsk vs = vs3v_avcc = vs5v 2.7v 3.0v 3.3v t amb = ?40c 5.6 ma 5.7 ma 5.8 ma t amb = 25c 6.6 ma 6.7 ma 6.8 ma t amb = 105c 7.6 ma 7.7 ma 7.8 ma -10.0 0.0 10 . 0 20.0 30.0 40.0 50 .0 60.0 70 .0 -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2. 0 distance from interferin g to receivin g si g nal ( mhz ) blocking level (dbc)
12 4596a?rke?05/06 ata5745/ATA5746 [preliminary] figure 2-7. narrow-band 3-db blocking characteristic at 315 mhz figure 2-8. wide-band 3-db blocking characteristic at 315 mhz table 2-8 shows the blocking performance measured relative to ?102 dbm for some frequen- cies. note that sometimes the blocking is measured relative to the sensitivity level 104 dbm (denoted dbs), instead of the carrier ?102 dbm (denoted dbc) table 2-8. blocking 3 db above sensitivity level with ber < 10 ?3 frequency offset blocking level blocking +1.5 mhz ?44.5 dbm 57.5 dbc, 60.5 dbs ?1.5 mhz ?44.5 dbm 57.5 dbc, 60.5 dbs +2 mhz ?39.0 dbm 63 dbc, 66 dbs ?2 mhz ?36.0 dbm 66 dbc, 69 dbs +3 mhz ?34.5 dbm 67.5 dbc, 70.5 dbs ?3 mhz ?34.5 dbm 67.5 dbc, 70.5 dbs +20 mhz ?28.0 dbm 74 dbc, 77 dbs ?20 mhz ?28.0 dbm 74 dbc, 77 dbs -10.0 0.0 10 . 0 20.0 30.0 40.0 50 .0 60.0 70 .0 80.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0 5. 0 distance from interfering to receiving signal (mhz) blocking level (dbc) -10.0 0.0 10 . 0 20.0 30.0 40.0 50 .0 60.0 70 .0 80.0 -50.0 -40.0 -30.0 -20.0 -10.0 0.0 10.0 20.0 30.0 40.0 50. 0 distance from interfering to receiving signal (mhz) blocking level (dbc)
13 4596a?rke?05/06 ata5745/ATA5746 [preliminary] the ata5745/ATA5746 can also receive fsk and ask modulated signals if they are much higher than the i1dbcp. it can typically receive useful signals at ? 10 dbm. this is often referred to as the nonlinear dynamic range (that is, the maximum to minimum receiving signal), and is 95 db for 10 kbits/s manchester (fsk). this value is useful if the transmitter and receiver are very close to each other. 2.7 in-band disturbers, data filter, quasi-peak detector, data slicer if a disturbing signal falls into the received band, or if a blocker is not a continuous wave, the performance of a receiver strongly depends on the circuits after the if filter. hence, the demod- ulator, data filter, and data slicer are important. the data filter of the ata5745/ATA5746 functions also as a quasi-peak detector. this results in a good suppression of above mentioned disturbers and exhibits a good carrier-to-noise perfor- mance. the required useful-signal-to-dis turbing-signal ratio, at a ber of 10 ?3, is less than 14 db in ask mode and less than 3 db (br_range_0 to br_range_2) and 6 db (br_range_3) in fsk mode. due to the many different possible waveforms, these numbers are measured for the signal, as well as for disturbers, with peak amplitude values. note that these values are worst-case values and are valid for any type of modulation and modulating frequency of the dis- turbing signal, as well as for the receiving signal. for many combinations, lower carrier-to-disturbing-signal ratios are needed. 2.8 rssi output the output voltage of the pin rssi is an analog voltage, proportional to the input power level. using the rssi output signal, the signal strength of different transmitters can be distinguished. the usable dynamic range of the rssi amplifier is 65 db, the input power range p(rf in ) is ?110 dbm to ?45 dbm, and the gain is 15 mv/db. figure 2-9 shows the rssi characteristic of a typical device at 315 mhz with vs3v_avcc = vs5v = 2.7v to 3.3v and t amb = ?40c to +105c with a matched input as shown in table 2-2 and figure 2-1 on page 6 . at 433.92 mhz, 1 db more signal level is nee ded for the same rssi results. figure 2-9. typical rssi characteristic at 315 mhz versus temperature and supply voltage 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 pin ( dbm ) v_rssi (v) max; +9db 2.7v, -40?c 3.0v, -40?c 3.3v, -40?c 2.7v, 27?c 3.0v, 27?c 3.3v, 27?c 2.7v, 105? c 3.0v, 105? c 3.3v, 105? c min; -9db
14 4596a?rke?05/06 ata5745/ATA5746 [preliminary] as can be seen in figure 2-9 on page 13 , for single devices there is a variance over temperature and supply voltage range of 3 db. the total variance over production, temperature, and supply voltage range is 9 db. 2.9 frequency synthesizer the lo generates the carrier frequency for the mixer via a pll synthesi zer. the xto (crystal oscillator) generates the reference frequency f xto . the vco (voltage-controlled oscillator) gen- erates the drive voltage frequency f lo for the mixer. f lo is divided by the factor 24 (ATA5746) or 32 (ata5745). the divided frequency is compared to f xto by the phase frequency detector. the current output of the phase frequency detector is connected to the fully integrated loop filter, and thereby generates the control voltage for the vco. by means of that configuration, the vco is controlled in a way, such that f lo /24 (f lo / 32) is equal to f xto . if f lo is determined, f xto can be calculated using the following formula: f xto =f lo / 24 (f xto =f lo / 32). the synthesizer has a phase noise of ?130 dbc/hz at 3 mhz and spurs of ?75 dbc. care must be taken with the harmonics of the clk output signal, as well as with the harmonics produced by a microprocessor clocked using the signal, as these harmonics can disturb the reception of signals. 3. xto the xto is an amplitude-regulated pierce osci llator type with external load capacitances (2 16 pf). due to additional internal and board parasitics (c p ) of approximately 2 pf on each side, the load capacitance amounts to 2 18 pf (9 pf total). the xto oscillati on frequency f xto is the reference frequency for the integer-n synthesizer. when designing the system in terms of receiving and transmitting frequency offset, the accuracy of the crystal and xto have to be considered. the xto?s additional pulling (including the r m tolerance) is only 5 ppm. the xtal versus tem- perature, aging, and tolerances is then the main source of frequency er ror in the local oscillator. the xto frequency depends on xtal properties and the load capacitances c l1,2 at pin xtal1 and xtal2. the pulling (p) of f xto from the nominal f xtal is calculated using the following for- mula: c m , the crystal's motional capacitance; c 0 , the shunt capacitance; and c ln , the nominal load capacitance of the xtal, are found in the datasheet. c l is the total actual load capacitance of the crystal in the circuit, and consists of c l1 and c l2 connected in series. p c m 2 ------- - c ln c l ? c o c ln + () c o c l + () --------------------------------------------------------------- 10 -6 ppm =
15 4596a?rke?05/06 ata5745/ATA5746 [preliminary] figure 3-1. crystal equivalent circuit with c m 10 ff, c 0 1.0 pf, c ln = 9 pf and c l1,2 = 16 pf 1%, the pulling amounts to p 1 ppm. the c 0 of the xtal has to be lower than c lmin / 2 = 7.9 pf for a pierce oscillator type in order to not enter the steep region of pulling versus load capacitance where there is risk of an unstable oscillation. to ensure proper start-up behavior, the small si gnal gain and the negative resistance provided by this xto at start is very larg e. for example, oscillation starts up even in the worst case with a crystal series resistance of 1.5 k ? at c 0 2.2 pf with this xto. the negative resistance is approximately given by with z 1 and z 2 as complex impedances at pins xtal1 and xtal2, hence z 1 =?j/(2 p f xto c l1 )+5 ? and z 2 =?j/(2 p f xto c l2 )+5 ? . z 3 consists of crystal c 0 in parallel with an internal 110-k ? resistor, hence z 3 =?j/(2 p f xto c 0 )/110k ? , gm is the internal transconductance between xtal1 and xtal2, with typically 20 ms at 25c. with f xto = 13.5 mhz, gm = 20 ms, c l = 9 pf, and c 0 = 2.2 pf, this results in a negative resis- tance of about 2 k ? . the worst case for technology, supply voltage, and temperature variations is then always higher than 1.4 k ? for c 0 2.2 pf. due to the large gain at start, the xto is able to meet a very low start- up time. the oscillation start-up time can be estimated with the time constant . after 10 to 20 , an amplitude detector detects the oscillation amplitude and sets xto_ok to high if the amplitude is large enough; this activates the clk_out output if it is enabled via the pins clk_out_ctrl0 and clk_out_ctrl1. note that the necessary conditions of the dvcc voltage also have to be fulfilled. it is recommended to use a crystal with c m = 3.0 ff to 10 ff, c ln =9pf, r m <120 ? and c 0 = 1.0 pf to 2.2 pf. c 0 c l2 c l1 c m l m r m c l = c l1 c l2 / (c l1 + c l2 ) xtal crystal equivalent circuit re zxtocore {} re z 1 z 3 z 2 z 3 z 1 z 3 gm + + z 1 z 2 z 3 z 1 z 2 gm +++ ---------------------------------------------------------------------------------------- - ?? ?? ?? = 2 4 2 f xtal 2 c m re z xtocore () r m + () ------------------------------------------------------------------------------------------------------------------ - =
16 4596a?rke?05/06 ata5745/ATA5746 [preliminary] lower values of c m can be used, slightly increasing the start-up time. lower values of c 0 or higher values of c m (up to 15 ff) can also be used, wi th only little influence on pulling. figure 3-2. xto block diagram the relationship between f xto and the f rf is shown in table 3-1 . attention must be paid to the harmonics of the clk_out output signal f clk_out as well as to the harmonics produced by an microprocessor clocked with it, since these harmonics can disturb the reception of signals if they get to the rf input. if the clk_out signal is used, it must be carefully laid out on the application pcb. the supply voltage of the microcontroller must also be carefully blocked. table 3-1. calculation of f rf frequency [mhz] f xto [mhz] f rf 433.92 (ata5745) 13.57375 f xto x 32 ? 440 khz 315.0 (ATA5746) 13.1433 f xto x 24 ? 440 khz c l2 c l1 f dclk f fxto clk_out_ctrl1 clk_out_ctrl0 xto_ok xtal1 xtal2 clk_out amplitude detector divider /16 & divider /3, /6, /12
17 4596a?rke?05/06 ata5745/ATA5746 [preliminary] 3.1 pin clk_out pin clk_out is an output to clock a connected microcontroller. the clock is available in standby and active modes. the frequency f clk_out can be adjusted via the pins clk_out_ctrl0 and clk_ out_ctrl1, and is ca lculated as follows: the signal at clk_out output has a nominal 50% duty cycle. to save current, it is recom- mended that clk_out be switched off during standby mode. 3.2 basic clock cycle of the digital circuitry the complete timing of the digital circuitry is derived from one clock. as seen in figure 3-2 on page 16 , this clock cycle, t dclk , is derived from the crystal osc illator (xto) in co mbination with a divider. t dclk controls the following applic ation relevant parameters: - debouncing of the data signal stream - start-up time of the rx signal path the start-up time and the debounce characteristic depend on the selected bit rate range (br_range) which is defined by pins br0 and br1. the clock cycle t xdclk is defined by the fol- lowing formulas for further reference: br_range ? br_range 0: t xdclk = 8 t dclk br_range 1: t xdclk = 4 t dclk br_range 2: t xdclk = 2 t dclk br_range 3: t xdclk = 1 t dclk table 3-2. setting of f clk_out clk_out_ctrl1 clk_out_ctrl0 function 00 clock on pin clk_out is switched off (low level on pin clk_out) 01 f clk_out =f xto /3 10 f clk_out =f xto /6 11 f clk_out =f xto /12 f dclk f xto 16 ----------- =
18 4596a?rke?05/06 ata5745/ATA5746 [preliminary] 4. sensitivity reduction the output voltage of the rssi amplifier is internally compared to a threshold voltage v th_red . v th_red is determined by the value of the external resistor r sense . r sense is connected between the pins sense and vs3v_avcc (see figure 10-1 on page 28 ). the output of the comparator is fed into the digital control logic. by this means , it is possible to operate the receiver at a lower sensitivity. if the level on input pin sen se_ctrl is low, the receiver operates at full sensitivity. if the level on input pin sense_ctrl is high, the receiver operates at a lower sensitivity. the reduced sensitivity is defined by the value of r sense , the maximum sensitivity by the sig- nal-to-noise ratio of the lna input. the reduced sensitivity depends on the signal strength at the output of the rssi amplifier. since different rf input networks may exhibit slig htly different values for the lna gain, the sen- sitivity values given in the electrical characte ristics refer to a specific input matching. this matching is illustrated in figure 2-1 on page 6 and exhibits the best possible sensitivity. if the sensitivity reduction feature is not used, pin sense can be left open, pin sense_ctrl must be set to gnd. to operate with reduced sensitivity, pin sense_ctrl must be set to high before the rx signal path will be enabled by setti ng pin rx to high (see figure 4-1 on page 19 ). as long as the rssi level is lower than v th_red (defined by the external resistor r sense ) no data stream is available on pin data_out (low level on pin da ta_out). an internal rs flip-flo p will be set to high the first time the rssi voltage crosses v th_red , and from then on the data stream will be available on pin data_out. from then on the receiver also works wit h full sensitivity. th is makes sure that a telegram will not be interrupted if the rssi level varies during th e transmission. the rs flip-flop can be set back, and thus the receiver switched ba ck to reduced sensitivity, by generating a pos- itive pulse on pin ask_nfsk (see figure 4-2 on page 19 ). in fsk mode, operating with reduced sensitivity follows the same way.
19 4596a?rke?05/06 ata5745/ATA5746 [preliminary] figure 4-1. reduced sensitivity active figure 4-2. restart reduced sensitivity rssi rx data_out sense_ctrl ask_nfsk enable t startup_pll v th_red t startup_sig_proc rssi rx sense_ctrl data_out ask_nfsk enable v th_red t startup_sig_proc
20 4596a?rke?05/06 ata5745/ATA5746 [preliminary] 5. power supply figure 5-1. power supply the supply voltage range of the ata5745/ATA5746 is 2.7v to 3.3v or 4.5v to 5.5v. pin vs3v_avcc is the supply voltage input for the range 2.7v to 3.3v, and is used in battery applications using a single lithiu m 3v cell. pin vs5v is the voltage input for the range 4.5v to 5.5v (car applications) in this case the volt age regulator v_reg regu lates vs3v_avcc to typi- cally 3.0v. if the voltage regulator is active, a blocking capacitor of 2.2 f has to be connected to vs3v_avcc (see figure 10-1 on page 28 ). dvcc is the internal operating voltage of the digital control logic and is fed via the switch sw_dvcc by vs3v_avcc. dvcc must be blocked on pin dvcc with 68 nf (see figure 9-1 on page 27 and figure 10-1 on page 28 ). pin rx is the input to activate the rx signal processing and set the receiver to active mode. 5.1 off mode a low level on pin rx and enable will set the rece iver to off mode (low power mode). in this mode, the crystal oscillator is shut down and no clock is available on pin clk_out. the receiver is not sensitive to a transmitter signal in this mode. 5.2 standby mode the receiver activates the standby mode if pin enable is set to ?1?. in standby mode, the xto is running and the clock on pin clk_out is available after the start-up time of the xto has elapsed (dependent on pin clk_out_ctrl0 and clk_out_ctrl1). during standby mode, the receiv er is not sensitive to a transmitter signal. in standby mode, the rx signal path is disabled and the power consumption i standby is typically 50 a (clk_out output off, vs3v_avcc = vs5v = 3v). the exact value of this current is strongly dependent on the application and the exact operation mode, therefore check the sec- tion ?electrical characteristics: general? on page 29 for the appropriate application case. v_reg 3.0v typ. sw_dvcc out rx dvcc vs5v vs3v_avcc in en table 5-1. standby mode rx enable function 00 off mode table 5-2. standby mode rx enable function 0 1 standby mode
21 4596a?rke?05/06 ata5745/ATA5746 [preliminary] figure 5-2. standby mode (clk_out_ctrl0 or clk_out_ctrl1 = 1) 5.3 active mode the active mode is enabled by setting the level on pin rx to high. in active mode, the rx signal path is enabled and if a valid signal is present it will be transferred to the connected microcontroller. during t startup_pll the pll is enabled and starts up. if the pll is locked, the signal processing circuit starts up (t startup_sig_proc ). after the start-up time, all circuits are in stable condition and ready to receive. the duration of the start-up sequence depends on the selected bit rate range. figure 5-3. active mode clk_out enable standby mode t xto_startup table 5-3. active mode rx enable function 1 1 active mode data_out valid t startup_pll t startup_sig_proc i startup_pll i active i active i standby startup clk_out rx data_out enable standby mode active mode
22 4596a?rke?05/06 ata5745/ATA5746 [preliminary] table 5-4. start-up time br1 br0 ata5745 (433.92 mhz) ATA5746 (315 mhz) t startup_pll t startup_sig_proc t startup_pll t startup_sig_proc 00 261 s 1096 s 269 s 1132 s 0 1 644 s 665 s 1 0 417 s 431 s 1 1 304 s 324 s table 5-5. modulation scheme ask_nfsk rf in at pin lna_in level at pin data_out 0 f fsk_h 1 f fsk_l 0 1 f ask on 1 f ask off 0
23 4596a?rke?05/06 ata5745/ATA5746 [preliminary] 6. bit rate ranges configuration of the bit rate ranges is carried out via the two pins br0 and br1. the microcon- troller uses these two interface lines to set th e corner frequencies of the band-pass data filter. switching the bit rate ranges while the rf front end is in active mode can be done on the fly and will not take longer than 100 s if done while remaining in either ask or fsk mode. if the modu- lation scheme is changed at the same time, the switching time is (t startup_sig_proc , see figure 7-1 on page 25 ). each br_range is defined by a minimum edge-to-edge time. to maintain full sen- sitivity of the receiver, edge-to-edge transition ti mes of incoming data should not be less than the minimum for the selected br_range. table 6-1. br ranges ask br1 br0 br_range recommended bit rate (manchester) (1) minimum edge-to-edge time period t ee of the data signal (2) edge-to-edge time period t ee of the data signal du ring the start-up period (3) 0 0 br_range0 1.0 kbit/s to 2.5 kbits/s 200 s 200 s to 500 s 0 1 br_range1 2.0 kbits/s to 5.0 kbits/s 100 s 100 s to 250 s 1 0 br_range2 4.0 kbits/s to 10.0 kbits/s 50 s 50 s to 125 s 1 1 br_range3 8.0 kbits/s to 10.0 kbits/s 50 s 50 s to 62.5 s table 6-2. br ranges fsk br1 br0 br_range recommended bit rate (manchester) (1) minimum edge-to-edge time period t ee of the data signal (2) edge-to-edge time period t ee of the data signal du ring the start-up period (3) 0 0 br_range0 1.0 kbit/s to 2.5 kbits/s 200 s 200 s to 500 s 0 1 br_range1 2.0 kbits/s to 5.0 kbits/s 100 s 100 s to 250 s 1 0 br_range2 4.0 kbits/s to 10.0 kbits/s 50 s 50 s to 125 s 1 1 br_range3 8.0 kbits/s to 20.0 kbits/s 25 s 25 s to 62.5 s note: if during the start-up period (t startup_pll +t startup_sig_proc ) there is no rf signal, the data filter se ttles to the noise floor, leading to noise on pin data_out. notes: 1. as can be seen, a bit stream of, for example, 2.5 kb its/s can be received in br_range0 and br_range1 (overlapping br_ranges). to get the full sensitivity, always use the lowest possible br_range (here, br_range0). the advantage in the next higher br_range (br_range1) is the shorter start-up period, meaning lower current consumption during polling mode. thus, it is a decision betwee n sensitivity and cu rrent consumption. 2. the receiver is also capable of re ceiving non-manchester-modula ted signals, such as pw m, ppm, vpwm, nrz. in ask mode, the header and blanking periods occurring in keeloq-like protocols (up to 52 ms) are supported. 3. to ensure an accurate settling of th e data filter during the start-up period ( t startup_pll + t startup_sig_proc ), the edge-to-edge time t ee of the data signal (preamble) must be inside the given limits during this period.
24 4596a?rke?05/06 ata5745/ATA5746 [preliminary] figure 6-1. examples of supported modulation formats figure 6-2. supported header and blanking periods t ee logic 1 nrz: logic 0 t ee t ee t ee t ee t ee logic 1 ppm: logic 0 t ee t ee t ee t ee t ee t ee logic 1 pwm: logic 0 t ee t ee t ee t ee t ee logic 1 man: logic 0 t ee t ee t ee logic 1 logic 0 vpwm: on transition low to high t ee t ee t ee t ee logic 1 logic 0 on transition high to low preamble header data burst guard time data burst
25 4596a?rke?05/06 ata5745/ATA5746 [preliminary] 7. ask_nfsk the ask_nfsk pin allows the microcontroller to rapidly switch the rf front end between demodulation modes. a logic 1 on this pin selects ask mode, a nd a logic 0 fsk mode. the time to change modes (t startup_sig_proc ) depends on the bit rate range being selected (not current bit rate range) and is given in table 5-4 on page 22 . this response time is specified for applications that require an ask preamble followed by fsk data (for typical tpm applications). during t startup_sig_proc , the level on pin data_out is low. figure 7-1. ask preamble 2.4 kbits/s followe d by fsk data 9.6 kbits/s rx ask_nfsk data_out data valid br3 data valid br0 br0 br1 enable t startup_sig_proc
26 4596a?rke?05/06 ata5745/ATA5746 [preliminary] 8. polling current calculation figure 8-1. polling cycle in an rke and tpm system, the averag e chip current in polling mode, i polling , is an important parameter. the polling period must be controlled by the connected microcontroller via the pins enable and rx. the polling current can be calculated as follows: i polling =(t startup_pll /t polling_period ) i startup_pll +(t startup_sig_proc /t polling_period ) i active + (t bitcheck /t polling_period ) i active +(t polling_period ?t startup_pll ?t startup_sig_proc ?t bitcheck )/ t polling_period i standby t startup_pll : depends on 315 mhz/433.92 mhz application. t startup_sig_proc : depends on 315 mhz/433.92 mhz application and the selected bit rate range. t bitcheck : depends on the signal bit rate (1 / signal_bit_rate). t polling_period : depends on the transmitter telegram (preburst). i startup_pll : depends on 3v or 5v application and the setting of pin clk_out. i active : depends on 3v or 5v application, ask or fsk mode and the setting of pin clk_out. i standby : depends on 3v or 5v application and the setting of pin clk_out. example:- 315-mhz application (ATA5746), bit rate: 9.6 kbits/s, t polling_period =8ms --> t startup_pll = 269 s --> t startup_sig_proc = 324 s (bit rate range 3) --> t bitcheck = 104 s 3v application; ask mode, clk_out disabled --> i startup_pll =4.5ma --> i active =6.5ma --> i standby =0.05ma --> i polling = 0.545 ma i standby i standby i active i startup_pll i active i startup_pll rx i supply enable t bitcheck (= 1 / signal_bitrate (average) t startup_pll (startup rf-pll) t startup_sig_proc (startup signal processing)
27 4596a?rke?05/06 ata5745/ATA5746 [preliminary] 9. 3v application figure 9-1. 3v application note: paddle (backplane) must be connected to gnd test2 test1 enable clk_out vs5v gnd vs3v_avcc dvcc xtal1 xtal2 br1 rx br0 ask_nfsk cdem data_out clk_out_ctrl0 clk_out_ctrl1 output output output output input output vcc vss test3 lna_in lna_gnd sense sense_ctrl rssi rf in 18 pf microcontroller ata5745/ ATA5746 18 pf 68 nf 15 nf 2.2 pf 68 nh/36 nh 315 mhz/433.92 mh z 68 nf v cc = 2.7v to 3.3v
28 4596a?rke?05/06 ata5745/ATA5746 [preliminary] 10. 5v application figure 10-1. 5v application with re duced/full sensitivity note: paddle (backplane) must be connected to gnd test2 test1 enable clk_out vs5v gnd vs3v_avcc dvcc xtal1 xtal2 br1 rx br0 ask_nfsk cdem data_out clk_out_ctrl0 clk_out_ctrl1 output output output output output input output vcc vss test3 lna_in lna_gnd sense sense_ctrl rssi rf in r sense 18 pf microcontroller ata5745/ ATA5746 18 pf 68 nf 15 nf 2.2 pf 2.2 f 68 nh/36 nh 315 mhz/433.92 mhz 68 nf v cc = 4.5v to 5.5v
29 4596a?rke?05/06 ata5745/ATA5746 [preliminary] 11. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . parameters symbol min. max. unit junction temperature t j +150 c storage temperature t stg ?55 +125 c ambient temperature t amb ?40 +105 c supply voltage vs5v v s +6 v esd (human body model esd s 5.1) every pin hbm ?4 +4 kv esd (machine model jedec a115a) every pin mm ?200 +200 v esd (field induced charge device model esd stm 5.3.1-1999) every pin fcdm ?500 +500 v maximum input level, input matched to 50 ? p in_max 0dbm 12. thermal resistance parameters symbol value unit junction ambient r thja 25 k/w 13. electrical charac teristics: general all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs3v_avcc =v vs5v = 2.7v to 3.3v, and v vs5v = 4.5v to 5.5v. typical values are given at v vs3v_avcc =v vs5v =3v, t amb = 25c, and f rf = 315 mhz unless otherwise specified. details about current consumption, timing, and digital pin properties can be found in the specific sections of th e ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* 1 off mode 1.1 supply current in off mode v vs3v_avcc =v vs5v 3v v vs5v =5v clk_out disabled 10, 11 10 i soff 2 2 a a a a 2 standby mode 2.1 rf operating frequency range ATA5746 14 f rf 313 317 mhz a ata5745 14 f rf 433 435 mhz a 2.2 supply current standby mode xto running v vs3v_avcc =v vs5v 3v clk_out disabled 10,11 i standby 50 100 a a xto running v vs5v =5v clk_out disabled 10,11 i standby 50 100 a a 2.3 system start-up time xto startup xtal: c m = 5 ff, c 0 = 1.8 pf, r m = 15 ? t xto_startup 0.3 0.8 ms a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in parenthesis were measured with rf_in matched to 50 ? according to figure 2-1 on page 6 with component values as in table 2-2 on page 6 (rf in ).
30 4596a?rke?05/06 ata5745/ATA5746 [preliminary] 2.4 active mode start-up time from standby mode to active mode br_range_3 ata5745 ATA5746 t startup_pll + t startup_sig_proc 565 593 s s a 3 active mode 3.1 supply current active mode v vs3v_avcc =v vs5v =3v ask mode clk_out disabled sense_ctrl = 0 10,11 i active 6.5 ma a v vs3v_avcc =v vs5v =3v fsk mode clk_out disabled sense_ctrl = 0 10,11 i active 6.7 ma a v vs5v =5v ask mode clk_out disabled sense_ctrl = 0 10 i active 6.7 ma a v vs5v =5v fsk mode clk_out disabled sense_ctrl = 0 10 i active 6.9 ma a 3.2 supply current polling mode v vs3v_avcc =v vs5v =3v t polling_period = 8 ms br_range_3, ask mode, clk_out disabled data rate = 9.6 kbits/s 10,11 i polling 545 a c 3.3 input sensitivity fsk f rf = 315 mhz fsk deviation f dev = 38 khz ber = 10 ? 3 t amb = 25c bit rate 9.6 kbits/s br2 (14) p ref_fsk ?103 ?105 ?106.5 dbm b bit rate 2.4 kbits/s br0 (14) p ref_fsk ?106 ?108 ?109.5 dbm b fsk deviation 18 khz to 50 khz bit rate 9.6 kbits/s br2 (14) p ref_fsk ?101 dbm b bit rate 2.4 kbits/s br0 (14) p ref_fsk ?104 dbm b 3.4 input sensitivity ask f rf = 315 mhz ask 100% level of carrier, ber = 10 ? 3 t amb = 25c bit rate 9.6 kbits/s br2 (14) p ref_ask ?109 ?111 ?112.5 dbm b bit rate 2.4 kbits/s br0 (14) p ref_ask ?112 ?114 ?115.5 dbm b 13. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs3v_avcc =v vs5v = 2.7v to 3.3v, and v vs5v = 4.5v to 5.5v. typical values are given at v vs3v_avcc =v vs5v =3v, t amb = 25c, and f rf = 315 mhz unless otherwise specified. details about current consumption, timing, and digital pin properties can be found in the specific sections of th e ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in parenthesis were measured with rf_in matched to 50 ? according to figure 2-1 on page 6 with component values as in table 2-2 on page 6 (rf in ).
31 4596a?rke?05/06 ata5745/ATA5746 [preliminary] 3.5 sensitivity change at f rf =433.92mhz compared to f rf =315mhz f rf = 315 mhz to f rf =433.92mhz p=p ref_ask + ? p ref1 p=p ref_fsk + ? p ref1 (14) ? p ref1 +1 db b 3.6 sensitivity change versus temperature, supply voltage and frequency offset fsk f dev = 38 khz ? f offset 160 khz ask 100% ? f offset 160 khz p = p ref_ask + ? p ref1 + ? p ref2 p = p ref_fsk + ? p ref1 + ? p ref2 (14) ? p ref2 +4.5 ?1.5 b 3.7 reduced sensitivity r sense connected from pin sense to pin vs3v_avcc p ref_red dbm (peak level) r sense = 62 k ? f in = 433.92 mhz ?76 dbm c r sense = 82 k ? f in = 433.92 mhz ?88 dbm c r sense = 62 k ? f in = 315 mhz ?76 dbm c r sense = 82 k ? f in = 315 mhz ?88 dbm c reduced sensitivity variation over full operating range r sense = 62 k ? r sense = 82 k ? p red = p ref_red + p ? red ? p red ?10 +10 db 3.8 maximum frequency offset in fsk mode maximum frequency difference of f rf between receiver and transmitter in fsk mode (f rf is the center frequency of the fsk signal with f bit = 10 kbits/s f dev = 38 khz (14) ? f offset ?160 +160 khz b 3.9 supported fsk frequency deviation with up to 2 db loss of sensitivity. note that the tolerable frequency offset is 12 khz lower for f dev = 50 khz than for f dev = 38 khz, hence, ? f offset 148 khz (14) f dev 18 38 50 khz b 3.10 system noise figure f rf = 315 mhz (14) nf 6.0 9 db b f rf = 433.92 mhz (14) nf 7.0 10 db b 13. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs3v_avcc =v vs5v = 2.7v to 3.3v, and v vs5v = 4.5v to 5.5v. typical values are given at v vs3v_avcc =v vs5v =3v, t amb = 25c, and f rf = 315 mhz unless otherwise specified. details about current consumption, timing, and digital pin properties can be found in the specific sections of th e ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in parenthesis were measured with rf_in matched to 50 ? according to figure 2-1 on page 6 with component values as in table 2-2 on page 6 (rf in ).
32 4596a?rke?05/06 ata5745/ATA5746 [preliminary] 3.11 intermediate frequency f rf = 433.92 mhz f if 440 khz a f rf = 315 mhz f if 440 khz a 3.12 system bandwidth 3 db bandwidth this value is for information only! note that for crystal and system frequency offset calculations, ? f offset must be used. (14) sbw 435 khz a 3.13 system out-band 3rd-order input intercept point ? f meas1 = 1.8 mhz ? f meas2 = 3.6 mhz f rf = 315 mhz (14) iip3 ?24 dbm c f rf = 433.92 mhz (14) iip3 ?23 dbm c 3.14 system outband input 1-db compression point ? f meas1 = 1 mhz f rf = 315 mhz (14) i1dbcp ?31 ?36 dbm c f rf = 433.92 mhz (14) i1dbcp ?30 ?35 dbm c 3.15 lna input impedance f rf = 315 mhz 14 z in_lna (72.4 ? j298) ? c f rf = 433.92 mhz 14 z in_lna (55 ? j216) ? c 3.16 maximum peak rf input level, ask and fsk ber < 10 ? 3 , ask: 100% (14) p in_max +5 ?10 dbm c fsk: f dev = 38 khz (14) p in_max +5 ?10 dbm c 3.17 lo spurs at lna_in f < 1 ghz (14) ?57 dbm c f >1 ghz (14) ?47 dbm c f lo = 315.44 mhz 2 f lo 4 f lo (14) ?90 ?94 ?68 dbm c f lo = 434.36 mhz 2 f lo 4 f lo (14) ?92 ?88 ?58 dbm c 3.18 image rejection with the complete image band f rf = 315 mhz (14) 24 30 db a f rf = 433.92 mhz (14) 24 30 db a 3.19 useful signal to interferer ratio peak level of useful signal to peak level of interferer for ber < 10 ? 3 with any modulation scheme of interferer fsk br_ranges 0, 1, 2 (14) snr fsk0-2 23dbb fsk br_range_3 (14) snr fsk3 46dbb ask (p rf < p rfin_high )(14)snr ask 10 14 db b 13. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs3v_avcc =v vs5v = 2.7v to 3.3v, and v vs5v = 4.5v to 5.5v. typical values are given at v vs3v_avcc =v vs5v =3v, t amb = 25c, and f rf = 315 mhz unless otherwise specified. details about current consumption, timing, and digital pin properties can be found in the specific sections of th e ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in parenthesis were measured with rf_in matched to 50 ? according to figure 2-1 on page 6 with component values as in table 2-2 on page 6 (rf in ).
33 4596a?rke?05/06 ata5745/ATA5746 [preliminary] 3.20 rssi output dynamic range (14),17 d rssi 65 db a lower level of range f rf = 315 mhz f rf = 433.92 mhz (14),17 p rfin_low ?110 dbm a upper level of range f rf = 315 mhz f rf = 433.92 mhz (14),17 p rfin_high ?45 dbm a gain (14),17 15 mv/db a output voltage range (14),17 v rssi 350 1600 mv a 3.21 output resistance rssi pin 17 r rssi 81012.5k ? c 3.22 blocking sensitivity (ber = 10 ? 3 ) is reduced by 3 db if a continuous wave blocking signal at ? f is ? p block higher than the useful signal level (bit rate = 10 kbits/s, fsk, f dev 38khz, manchester code, br_range2) f rf = 315 mhz ? f 1.5 mhz ? f 2 mhz ? f 3 mhz ? f 10 mhz ? f 20 mhz (14) ? p block 57.5 63.0 67.5 72.0 74.0 dbc c f rf = 433.92 mhz ? f 1.5 mhz ? f 2 mhz ? f 3 mhz ? f 10 mhz ? f 20 mhz (14) ? p block 56.5 62.0 66.5 71.0 73.0 dbc c 3.23 cdem capacitor connected to pin 23 (cdem) 23 ?5% 15 +5% nf d 13. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs3v_avcc =v vs5v = 2.7v to 3.3v, and v vs5v = 4.5v to 5.5v. typical values are given at v vs3v_avcc =v vs5v =3v, t amb = 25c, and f rf = 315 mhz unless otherwise specified. details about current consumption, timing, and digital pin properties can be found in the specific sections of th e ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in parenthesis were measured with rf_in matched to 50 ? according to figure 2-1 on page 6 with component values as in table 2-2 on page 6 (rf in ).
34 4596a?rke?05/06 ata5745/ATA5746 [preliminary] 4xto 4.1 transconductance xto at start at startup; after startup the amplitude is regulated to v ppxtal 7,8 g m, xto 20 ms b 4.2 xto start-up time c 0 2.2 pf c m < 14 ff r m 120 ? 7,8 t xto_startup 300 800 s a 4.3 maximum c 0 of xtal 7,8 c 0max 3.8 pf d 4.4 pulling of lo frequency f lo due to xto, c l1 and c l2 versus temperature and supply changes 1.0 pf c 0 2.2 pf c m = 4.0 ff to 7.0 ff r m 120 ? 3 ? f xto ?5 +5 ppm c 4.5 amplitude xtal after startup c m =5ff, c 0 =1.8pf r m = 15 ? v(xtal1, xtal2) peak-to-peak value 7,8 v ppxtal 700 mvpp c v(xtal1) peak-to-peak value 7,8 v ppxtal 350 mvpp c 4.6 maximum series resistance r m of xtal at startup c 0 2.2 pf, small signal start impedance, this value is important for crystal oscillator startup 7,8 z xtal12_start ?1400 ?2000 ? b 4.7 maximum series resistance r m of xtal after startup c 0 2.2 pf c m < 14 ff 7,8 r m_max 15 120 ? b 4.8 nominal xtal load resonant frequency f rf = 433.92 mhz f rf =315mhz 7,8 f xtal 13.57375 13.1433 mhz d 4.9 external clk_out frequency clk_out_crtl1 = 0 clk_out_ctrl0 = 0 --> clk_out disabled 3f clk_out f clk disabled (low level on pin clk_out) mhz a clk_out_crtl1 = 0 clk_out_ctrl0 = 1 --> division ratio = 3 clk_out_crtl1 = 1 clk_out_ctrl0 = 0 --> division ratio = 6 clk_out_crtl1 = 1 clk_out_ctrl0 = 1 --> division ratio = 12 13. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs3v_avcc =v vs5v = 2.7v to 3.3v, and v vs5v = 4.5v to 5.5v. typical values are given at v vs3v_avcc =v vs5v =3v, t amb = 25c, and f rf = 315 mhz unless otherwise specified. details about current consumption, timing, and digital pin properties can be found in the specific sections of th e ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in parenthesis were measured with rf_in matched to 50 ? according to figure 2-1 on page 6 with component values as in table 2-2 on page 6 (rf in ). f clk f xto 3 ----------- = f clk f xto 6 ----------- = f clk f xto 12 ----------- =
35 4596a?rke?05/06 ata5745/ATA5746 [preliminary] f rf =433.92mhz clk_out division ratio = 3 = 6 = 12 clk_out has nominal 50% duty cycle 3f clk_out 4.52458 2.26229 1.13114 mhz d f rf =315mhz clk_out division ratio = 3 = 6 = 12 clk_out has nominal 50% duty cycle 3f clk_out 4.3811 2.190 1.0952 mhz d 4.10 dc voltage after startup v dc (xtal1, xtal2) xto running (standby mode, active mode) 7,8 v dcxto ?250 ?45 mv c 5 synthesizer 5.1 spurs in active mode at f clk_out , clk_out enabled (division ratio = 3) f rf =315mhz f rf =433.92mhz sp rx ?75 ?70 dbc c at f xto f rf =315mhz f rf =433.92mhz sp rx ?75 ?70 dbc a 5.2 phase noise at 3 mhz active mode f rf =315mhz f rf =433.92mhz l rx3m ?130 ?127 dbc/hz a 5.3 phase noise at 20 mhz active mode noise floor l rx20m ?135 ?132 dbc/hz b 6 microcontroller interface 6.1 clk_out output rise and fall time f clk_out <4.5mhz c l =10pf c l = load capacitance on pin clk_out 2.7v v vs5v 3.3v or 4.5v v vs5v 5.5v 20% to 80% v vs5v 3 t rise t fall 20 20 30 30 ns ns b 6.2 internal equivalent capacitance used for current calculation 3c clk_out 8pfb 13. electrical characterist ics: general (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs3v_avcc =v vs5v = 2.7v to 3.3v, and v vs5v = 4.5v to 5.5v. typical values are given at v vs3v_avcc =v vs5v =3v, t amb = 25c, and f rf = 315 mhz unless otherwise specified. details about current consumption, timing, and digital pin properties can be found in the specific sections of th e ?electrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter note: 1. pin numbers in parenthesis were measured with rf_in matched to 50 ? according to figure 2-1 on page 6 with component values as in table 2-2 on page 6 (rf in ).
36 4596a?rke?05/06 ata5745/ATA5746 [preliminary] 14. electrical characteri stic: 3v application all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs3v_avcc = v vs5v = 2.7v to 3.3v, and v vs5v = 4.5v to 5.5v. typical values are given at v vs3v_avcc = v vs5v = 3v, t amb = 25c, and f rf = 433.92 mhz unless otherwise spec ified. details about current consumption, timing, and digital pin properties can be found in the specific sections of th e ?electrical characteristics?. no. parameters test conditions pin symbol min. typ. max. unit type* 7 3v application 7.1 supply current in off mode v vs3v_avcc =v vs5v 3v clk_out disabled 10, 11 i soff 2aa 7.2 supported voltage range 3v application 10, 11 v vs3v_avcc , v vs5v 2.7 3.3 v a 7.3 current in standby mode (xto is running) v vs3v_avcc = v vs5v 3v external load c on pin clk_out = 12 pf clk enabled (division ratio 3) clk enabled (division ratio 6) clk enabled (division ratio 12) clk disabled 10, 11 i standby 420 290 220 50 a c c c a 7.4 current during t startup_pll v vs3v_avcc = v vs5v 3v clk disabled 10, 11 i startup_pll 4.5 ma c 7.5 current in active mode ask v vs3v_avcc = v vs5v 3v clk disabled sense_ctrl = 0 10, 11 i active 6.5 ma a 7.6 current in active mode fsk v vs3v_avcc = v vs5v 3v clk disabled sense_ctrl = 0 10, 11 i active 6.7 ma a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
37 4596a?rke?05/06 ata5745/ATA5746 [preliminary] 15. electrical characteri stics: 5v application all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs3v_avcc = v vs5v = 2.7v to 3.3v, and v vs5v = 4.5v to 5.5v. typical values are given at v vs3v_avcc = v vs5v = 3v, t amb = 25c, and f rf = 433.92 mhz unless otherwise spec ified. details about current consumption, timing, and digital pin properties can be found in the specific sections of th e ?electrical characteristics?. no. parameters test conditions pi n symbol min. typ. max. unit type* 85v application 8.1 supply current in off mode v vs5v =5v clk_out disabled 10 i soff 2aa 8.2 supported voltage range 5v application 10 v vs5v 4.5 5.5 v a 8.3 current in standby mode (xto is running) v vs5v 5v external load c on pin clk_out = 12 pf clk enabled (division ratio 3) clk enabled (division ratio 6) clk enabled (division ratio 12) clk disabled 10 i standby 700 490 370 50 a c c c a 8.4 current during t startup_pll v vs5v =5v clk disabled 10 i startup_pll 4.7 ma c 8.5 current in active mode ask v vs5v =5v clk disabled sense_ctrl = 0 10 i active 6.7 ma a 8.6 current in active mode fsk v vs5v =5v clk disabled sense_ctrl = 0 10 i active 6.9 ma a *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samples, d = design parameter
38 4596a?rke?05/06 ata5745/ATA5746 [preliminary] 16. digital timing characteristics all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs3v_avcc = v vs5v = 2.7v to 3.3v, and v vs5v = 4.5v to 5.5v. typical values are given at v vs3v_avcc = v vs5v = 3v, t amb = 25c, and f rf = 433.92 mhz unless otherwise spec ified. details about current consumption, timing, and digital pin properties can be found in the specific sections of the ?electrical characteristics? no. parameters test conditions pi n symbol min. typ. max. unit type* 9 basic clock cycle of the digital circuitry 9.1 basic clock cycle t dclk 16 / f xto 16 / f xto s a 9.2 extended basic clock cycle br_range_0 br_range_1 br_range_2 br_range_3 t xdclk 8 4 2 1 t dclk 8 4 2 1 t dclk s a 10 active mode 10.1 startup pll t startup_pll 15 s + 208 t dclk s a 10.2 startup signal processing br_range_0 br_range_1 br_range_2 br_range_3 t startup_sig_proc 929.5 545.5 353.5 257.5 t dclk 929.5 545.5 353.5 257.5 t dclk a 10.3 bit rate range ask br_range = br_range0 br_range1 br_range2 br_range3 fsk br_range = br_range0 br_range1 br_range2 br_range3 br_range 1.0 2.0 4.0 8.0 1.0 2.0 4.0 8.0 2.5 5.0 10.0 10.0 2.5 5.0 10.0 20.0 kbits/s a 10.4 minimum time period between edges at pin data_out br_range_0 br_range_1 br_range_2 br_range_3 24 t data_out_min 10 t xdclk s a 10.5 edge-to-edge time period of the data signal for full sensitivity in active mode br_range_0 br_range_1 br_range_2 br_range_3 t data_out 200 100 50 25 500 250 125 62.5 s b *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
39 4596a?rke?05/06 ata5745/ATA5746 [preliminary] 17. digital port characteristics all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs3v_avcc = v vs5v = 2.7v to 3.3v, and v vs5v = 4.5v to 5.5v. typical values are given at v vs3v_avcc = v vs5v = 3v, t amb = 25c, and f rf = 433.92 mhz unless otherwise spec ified. details about current consumption, timing, and digital pin properties can be found in the specific sections of the ?electrical characteristics? no. parameters test conditions pi n symbol min. typ. max. unit type* 11 digital ports 11.1 enable input - low level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 6v il 0.2 v s 0.12 v s va - high level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 6v ih 0.8 v s va 11.2 rx input - low level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 19 v il 0.2 v s 0.12 v s va - high level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 19 v ih 0.8 v s va 11.3 br0 input - low level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 20 v il 0.2 v s 0.12 v s va - high level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 20 v ih 0.8 v s va 11.4 br1 input - low level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 21 v il 0.2 v s 0.12 v s va - high level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 21 v ih 0.8 v s va 11.5 ask_nfsk input - low level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 22 v il 0.2 v s 0.12 v s va - high level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 22 v ih 0.8 v s va *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
40 4596a?rke?05/06 ata5745/ATA5746 [preliminary] 11.6 sense_ctrl input - low level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 16 v il 0.2 v s 0.12 v s va - high level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 16 v ih 0.8 v s va 11.7 clk_out_ctrl0 input - low level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 5v il 0.2 v s 0.12 v s va - high level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 5v ih 0.8 v s va 11.8 clk_out_ctrl1 input - low level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 4v il 0.2 v s 0.12 v s va - high level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 4v ih 0.8 v s va 11.9 test1 input test1 input must always be connected directly to gnd 200vd 11.10 test2 output test2 output must always be connected directly to gnd 100vd 11.11 test3 input test3 input must always be connected directly to gnd 18 0 0 v d 17. digital port characteristics (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs3v_avcc = v vs5v = 2.7v to 3.3v, and v vs5v = 4.5v to 5.5v. typical values are given at v vs3v_avcc = v vs5v = 3v, t amb = 25c, and f rf = 433.92 mhz unless otherwise spec ified. details about current consumption, timing, and digital pin properties can be found in the specific sections of the ?electrical characteristics? no. parameters test conditions pi n symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
41 4596a?rke?05/06 ata5745/ATA5746 [preliminary] 11.12 data_out output - saturation voltage low v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v i data_out = 250 a 24 v ol 0.15 0.4 v b - saturation voltage high v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v i data_out = ?250 a 24 v oh v vs ? 0.4 v vs ? 0.15 vb 11.13 clk_out output - saturation voltage low v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v i data_out = 100 a 3v ol 0.15 0.4 v b - saturation voltage high v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v i data_out = ?100 a 3v oh v vs ? 0.4 v vs ? 0.15 vb 17. digital port characteristics (continued) all parameters refer to gnd and are valid for t amb = ?40c to +105c, v vs3v_avcc = v vs5v = 2.7v to 3.3v, and v vs5v = 4.5v to 5.5v. typical values are given at v vs3v_avcc = v vs5v = 3v, t amb = 25c, and f rf = 433.92 mhz unless otherwise spec ified. details about current consumption, timing, and digital pin properties can be found in the specific sections of the ?electrical characteristics? no. parameters test conditions pi n symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter
42 4596a?rke?05/06 ata5745/ATA5746 [preliminary] 19. package information 18. ordering information extended type number package moq remarks ata5745-pxpw qfn24 1500 pcs 5 mm 5 mm, pb-free, 433.92 mhz ATA5746-pxpw qfn24 1500 pcs 5 mm 5 mm, pb-free, 315 mhz ata5745-pxqw qfn24 6000 pcs 5 mm 5 mm, pb-free, 433.92 mhz ATA5746-pxqw qfn24 6000 pcs 5 mm 5 mm, pb-free, 315 mhz specifications according to din technical drawings 0.3 0.4 0.9 0.1 not indicated tolerances 0.05 0.65 nom. 0.05 -0.05 +0 12 7 19 24 13 18 6 24 1 6 1 issue: 1; 15.11.05 drawing-no.: 6.543-5122.01-4 5 3.25 3.6 dimensions in mm package: qfn 24 - 5 x 5 exposed pad 3.6 x 3.6 (acc. jedec outline no. mo-220)
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